1. Field of the Invention
The present invention is concerned with random access memories of the type fabricated on a monolithic semiconductor chip using insulated gate semiconductor field-effect transistor technology, and more particularly relates to an improved structural layout for the principal components of each cell of an integrated circuit memory.
2. DESCRIPTION OF THE PRIOR ART
Large scale integration (LSI) techniques have brought about the construction of large arrays of binary storage elements on a single chip of silicon. These storage cells, typically using MOS technology, consist of multi-component circuits in a conventional bistable configuration. The immediate advantages of such semi-conductor storage devices are the high packing density and low power requirements. The insulated gate MOS transistor has been particularly exploited in this application area since it requires less substrate area (thereby increasing the packing density) and operates at very low power levels.
A well known memory cell circuit arrangement which utilizes insulated gate MOS field-effect transistors is the cross-coupled inverter stage as disclosed in U.S. Pat. No. 3,967,252. In that arrangement the gates of a pair of insulated gate MOS field-effect transistors are cross coupled to a true data mode and a complementary data node. Binary information stored within the cell is maintained by impedance means which are connected to the data nodes to maintain the potential at the gate of the transistors at a predetermined level which corresponds to the logic content of the cell. In the static random access memory cells shown in U.S. Pat. No. 3,967,252, there are two cross-coupled inverters comprising two load devices and four transistors. In an effort to minimize the substrate area required for a given number of memory cells, the two load devices in the static cell of each inverter have been fabricated as an integral portion of a polycrystalline silicon strip which interconnects a common drain supply node to a data node as disclosed and claimed in the above identified co-pending application.
There remains considerable interest in minimizing the dimensions of the cell structure of integrated circuit memories to provide improve performance and higher packing density. One prior art approach for minimizing the dimensions of a conventional cross-coupled inverter stage is illustrated in FIG. 7 of the drawing. In that arrangement, shared diffusion regions interconnect the principal components of the cell to corresponding components of adjacent cells in the same row or in the same column. Also, a pair of cells in a single column are energized from a common drain supply node. It is an object of the present invention to provide an improved structural layout for the principal components of each cell so that the shared diffusion regions and the common power supply nodes may be utilized more efficiently.